Figure 1 shows an example in which the host cPLD brings CNVST high while AVCC, DVCC and V DRIVE are still ramping. For SAR ADCs, the convert start pin, CNVST, may be sensitive to noise. No digital pin should toggle until all the power supplies have been fully established. For example, a high pulse on RESET, with a duration of at least 50 ns, is required to configure the AD7606 for normal operation after power up. After all power supplies are stable, the specified pulse or combination is applied to guarantee that the ADC starts in the intended state. Digital I/O State During Turn Onįor proper initialization, some SAR ADCs require certain logic states or sequences for digital functions such as reset, standby, or power-down. Read and follow the data sheet to ensure the proper sequence. The analog supplies are usually powered before the I/O supply, but this is not the case for all ADCs. To avoid forward biasing the ESD diodes and powering up the digital core in an unknown state, turn on the I/O supply before the interface circuitry. Application Note AN-932, Power Supply Sequencing, provides a good reference for designing supplies for these ADCs. Decoupling capacitors with short traces should be connected between the V IO pin and DGND.ĪDCs that operate with multiple supplies may have well-defined power-up sequences. The digital inputs should generally be between DGND − 0.3 V and V IO+ 0.3 V to avoid violating the absolute maximum ratings. This pin should be at the same voltage as the host interface (MCU, DSP, or FPGA) supply. Most SAR ADCs provide a separate digital I/O power-supply input, V IO or V DRIVE, which determines the operating voltage and logic compatibility of the interface. Digital I/O Power-Supply Level and Sequence This article discusses design techniques for reliable, integrated digital interfaces, including the digital power-supply level and sequence, I/O state during turn on, interface timing, signal quality, and errors caused by digital activity. Their advantages include small size, low power, no pipeline delay, and ease of use.Ī host processor can access or control the ADC via a variety of serial and parallel interfaces such as SPI, I 2C, and LVDS. Successive-approximation analog-to-digital converters, called SAR ADCs due to their successive-approximation register, are popular for applications requiring up to 18-bit resolution at up to 5 MSPS. Some switches have amazingly low series resistance but can only handle a few volts.Design Reliable Digital Interfaces for Successive-Approximation ADCs Generally speaking, switches with high voltage capability tend to have more resistance and/or cost more. The variation can cause unacceptable distortion under some conditions. When on the switch behaves like a resistor which varies with the applied voltage. When off the switch has a bit of leakage current and capacitance. The above-mentioned switches generally include level shifting so that a logic signal from 0-5V (say) can control a signal in the range +/-5V. If the signals are more like +/-15V range you can use something like an ADG5419 (there are many variations in the ADG*** series). If the signal is in the 0-5V or +/-2.5V range, you can use HC4053 type switches. The only analog switches I am aware of that behave as you suggest are designed for signals such as video.įor ordinary relatively low-frequency signals that are always positive or in a range such as +/-5V or +/-3.3V, you can use CD4053 type analog switches.
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